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ds008700-z8x0799 *this document is considered preliminary until the completion of full characterization. p reliminary p roduct s pecification * z8pe002 f eature -e nhanced z8p lus 0.5k rom o ne -t ime p rogrammable (otp) m icrocontroller features microcontroller core features ? all instructions execute in one 1-s instruction cycle with a 10-mhz crystal ? 512 bytes x 8 on-chip otp eprom memory ? 64 x 8 general-purpose registers (sram) ? six vectored interrupts with fixed priority ? operating speed: dc10 mhz ? six addressing modes: r , ir , x , d , ra , and im peripheral features ? 14 total input/output pins ? one 8-bit i/o port (port a) C i/o bit programmable C each bit programmable as push-pull or open-drain ? one 6-bit i/o port (port b) C i/o bit programmable C includes special functionality: stop-mode re- covery input, comparator inputs, selectable edge interrupts, and timer output ? one analog comparator ? 16-bit programmable watch-dog timer ( wdt ) ? software programmable timers configurable as: C two 8-bit standard timers and one 16-bit stan- dard timer C one 16-bit standard timer and one 16-bit pulse width modulator ( pwm ) timer additional features ? on-chip oscillator that accepts external crystal ( xtal ), ceramic resonator, inductor capacitor ( lc ), or external clocks ? external resistor capacitor ( rc ), an oscillator option ? voltage brown-out/power-on reset ( v bo / por ) ? programmable options: C eprom protect C rc oscillator ? power reduction modes: C halt mode with peripheral units active C stop mode for minimum power dissipation cmos/technology features ? low-power consumption ? 3.0v to 5.5v operating range @ 0 c to +70 c 4.5v to 5.5v operating range @ C40 c to +105 c ? 18-pin dip, soic, and 20-pin ssop packages general description the z8pe002 is the newest member of the z8plus micro- processor (mpu) family. similar to the z8e000 and z8e001, the z8pe002 offers easy software development, debug, prototyping, and an attractive one-time program- mable (otp) solution. for applications demanding powerful i/o capabilities, the z8pe002s dedicated input and output lines are grouped into two ports, and are configurable under software control. part number rom (bytes) ram* (bytes) speed (mhz) z8pe002 512 64 10 note: *general-purpose.
z8pe002 z8plus otp microcontroller zilog 2 p r e l i m i n a r y ds008700-z8x0799 general description (continued) both the 8-bit and 16-bit on-chip timers, with several user- selectable modes, administer real-time tasks such as count- ing/timing and i/o data communications. note: all signals with an overline are active low. for exam- ple, b/ w , in which word is active low; and b /w, in which byte is active low. power connections follow conventional descriptions below: connection circuit device power v cc v dd ground gnd v ss figure 1. functional block diagram two 8-bit timers or one 16-bit pwm timer one 16-bit standard timer interrupt control one analog comparator port a i/o alu flags wdt register pointer ram register file machine timing otp program memory program counter gnd xtal port b por & i/o v cc bo v
z8pe002 zilog z8plus otp microcontroller ds008700-z8x0799 p r e l i m i n a r y 3 figure 2. eprom programming mode block diagram address mux eprom option bits ad 9? ad 9? ad 9? d7? d7? z8plus core address counter pgm + test mode logic xtal adclk pgm data mux port a adclr/v pp
z8pe002 z8plus otp microcontroller zilog 4 p r e l i m i n a r y ds008700-z8x0799 pin description figure 3. 18-pin dip/soic pin identi?cation table 1. standard programming mode pin # symbol function direction 1C5 pb1Cpb5 port b, pins 1,2,3,4,5 input/output 6C9 pa7Cpa4 port a, pins 7,6,5,4 input/output 10C13 pa3Cpa0 port a, pins 3,2,1,0 input/output 14 v cc power supply 15 v ss ground 16 xtal2 crystal oscillator clock output 17 xtal1 crystal oscillator clock input 18 pb0 port b, pin 0 input/output pb1 pb2 pb3 pb4 pb5 pa7 pa6 pa5 pa4 pb0 xtal1 xtal2 v ss v cc pa0 pa1 pa2 pa3 18 18-pin dip/soic 1 910
z8pe002 zilog z8plus otp microcontroller ds008700-z8x0799 p r e l i m i n a r y 5 figure 4. 18-pin dip/soic pin identi?cation table 2. eprom programming mode pin # symbol function direction 1 pgm program mode input 2C4 gnd ground 5 adclr/v pp clear clock/program voltage input 6C9 d7Cd4 data 7,6,5,4 input/output 10C13 d3Cd0 data 3,2,1,0 input/output 14 v dd power supply 15 gnd ground 16 nc no connection 17 xtal1 1-mhz clock input 18 adclk address clock input pgm gnd gnd gnd adclr/v pp d7 d6 d5 d4 adclk xtal1 nc gnd v dd d0 d1 d2 d3 18 18-pin dip/soic 1 910
z8pe002 z8plus otp microcontroller zilog 6 p r e l i m i n a r y ds008700-z8x0799 pin description (continued) figure 5. 20-pin ssop pin identi?cation table 3. standard programming mode pin # symbol function direction 1C5 pb1Cpb5 port b, pins 1,2,3,4,5 input/output 6 nc no connection 7C10 pa7Cpa4 port a, pins 7,6,5,4 input/output 11C14 pa3Cpa0 port a, pins 3,2,1,0 input/output 15 nc no connection 16 v cc power supply 17 v ss ground 18 xtal2 crystal oscillator clock output 19 xtal1 crystal oscillator clock input 20 pb0 port b, pin 0 input/output pb1 pb2 pb3 pb4 pb5 nc pa7 pa6 pa5 pa4 pb0 xtal1 xtal2 v ss v cc nc pa0 pa1 pa2 pa3 20 20-pin ssop 1 10 11
z8pe002 zilog z8plus otp microcontroller ds008700-z8x0799 p r e l i m i n a r y 7 figure 6. 20-pin ssop pin identi?cation/eprom programming mode table 4. eprom programming mode pin # symbol function direction 1 pgm program mode input 2C4 gnd ground 5 adclr/v pp clear clock/program voltage input 6 nc no connection 7C10 d7Cd4 data 7,6,5,4 input/output 11C14 d3Cd0 data 3,2,1,0 input/output 15 nc no connection 16 v dd power supply 17 gnd ground 18 nc no connection 19 xtal1 1-mhz clock input 20 adclk address clock input pgm gnd gnd gnd adclr/v pp nc d7 d6 d5 d4 adclk xtal1 nc gnd v dd nc d0 d1 d2 d3 20 20-pin ssop 1 10 11
z8pe002 z8plus otp microcontroller zilog 8 p r e l i m i n a r y ds008700-z8x0799 absolute maximum ratings stresses greater than those listed under absolute maximum ratings can cause permanent damage to the device. this rat- ing is a stress rating only. functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. exposure to absolute maximum rating conditions for an extended period can affect device reliability. total power dissipation should not exceed 880 mw for the package. power dissipation is calculated as follows: parameter min max units note ambient temperature under bias C40 +105 c storage temperature C65 +150 c voltage on any pin with respect to v ss C0.6 +7 v 1 voltage on v dd pin with respect to v ss C0.3 +7 v voltage on pb5 pin with respect to v ss C0.6 v dd +1 v 2 total power dissipation 880 mw maximum allowable current out of v ss 40 ma 3 maximum allowable current into v dd 40 ma 3 maximum allowable current into an input pin C600 +600 a 4 maximum allowable current into an open-drain pin C600 +600 a 5 maximum allowable output current sunk by any i/o pin 25 ma maximum allowable output current sourced by any i/o pin 25 ma maximum allowable output current sunk by port a 40 ma 3 maximum allowable output current sourced by port a 40 ma 3 maximum allowable output current sunk by port b 40 ma 3 maximum allowable output current sourced by port b 40 ma 3 notes: 1. applies to all pins except the pb5 pin and where otherwise noted. 2. there is no input protection diode from pin to v dd . 3. peak current. do not exceed 25ma average current in either direction. 4. excludes xtal pins. 5. device pin is not at an output low state. total power dissipation = v dd x [i dd C (sum of i oh )] + sum of [(v dd C v oh ) x i oh ] + sum of (v ol x i ol )
z8pe002 zilog z8plus otp microcontroller ds008700-z8x0799 p r e l i m i n a r y 9 standard test conditions the characteristics listed below apply for standard test con- ditions as noted. all voltages are referenced to ground. pos- itive current flows into the referenced pin (figure 7). capacitance t a = 25oc, v cc = gnd = 0v, f = 1.0 mhz, unmeasured pins returned to gnd. figure 7. test load diagram from output under test 150 pf parameter min max input capacitance 0 12 pf output capacitance 0 12 pf i/o capacitance 0 12 pf
z8pe002 z8plus otp microcontroller zilog 10 p r e l i m i n a r y ds008700-z8x0799 dc electrical characteristics table 5. dc electrical characteristics t a = 0oc to +70oc standard temperatures typical 2 @ 25c sym parameter v cc 1 min max units conditions notes v ch clock input high voltage 3.0v 0.7v cc v cc +0.3 1.3 v driven by external clock generator 5.5v 0.7v cc v cc +0.3 2.5 v driven by external clock generator v cl clock input low voltage 3.0v v ss C0.3 0.2v cc 0.7 v driven by external clock generator 5.5v v ss C0.3 0.2v cc 1.5 v driven by external clock generator v ih input high voltage 3.0v 0.7v cc v cc +0.3 1.3 v 5.5v 0.7v cc v cc +0.3 2.5 v v il input low voltage 3.0v v ss C0.3 0.2v cc 0.7 v 5.5v v ss C0.3 0.2v cc 1.5 v v oh output high voltage 3.0v v cc C0.4 3.1 v i oh = C2.0 ma 5.5v v cc C0.4 4.8 v i oh = C2.0 ma v ol1 output low voltage 3.0v 0.6 0.2 v i ol = +4.0 ma 5.5v 0.4 0.1 v i ol = +4.0 ma v ol2 output low voltage 3.0v 1.2 0.5 v i ol = +6 ma 5.5v 1.2 0.5 v i ol = +12 ma v offset comparator input offset voltage 3.0v 25.0 10.0 mv 5.5v 25.0 10.0 mv i il input leakage 3.0v C1.0 2.0 0.064 a v in = 0v, v cc 5.5v C1.0 2.0 0.064 a v in = 0v, v cc i ol output leakage 3.0v C1.0 2.0 0.114 a v in = 0v, v cc 5.5v C1.0 2.0 0.114 a v in = 0v, v cc v icr comparator input common mode voltage range 3.0v v ss C0.3 v cc C1.0 v 3 5.5v v ss C0.3 v cc C1.0 v 3 r pb5 pb5 pull-up resistor 3.0v 100 200 kohm 4 5.5v 100 200 v lv v cc low-voltage protection 2.45 2.85 2.60 v notes: 1. the v cc voltage speci?cation of 3.0v guarantees 3.0v; the v cc voltage speci?cation of 5.5v guarantees 5.0v 0.5v. 2. typical values are measured at v cc = 3.3v and v cc = 5.0v; v ss = 0v = gnd. 3. for the analog comparator input when the analog comparator is enabled. 4. no protection diode is provided from the pin to v cc . external protection is recommended. 5. all outputs are unloaded and all inputs are at the v cc or v ss level. 6. cl1 = cl2 = 22 pf. 7. same as note 5, except inputs are at v cc .
z8pe002 zilog z8plus otp microcontroller ds008700-z8x0799 p r e l i m i n a r y 11 i cc supply current 3.0v 2.5 2.0 ma @ 10 mhz 5,6 5.5v 6.0 3.5 ma @ 10 mhz 5,6 i cc1 standby current 3.0v 2.0 1.0 ma halt mode v in = 0v, v cc @ 10 mhz 5,6 5.5v 4.0 2.5 ma halt mode v in = 0v, v cc @ 10 mhz 5,6 i cc2 standby current 500 150 na stop mode v in = 0v, v cc 7 table 5. dc electrical characteristics (continued) t a = 0oc to +70oc standard temperatures typical 2 @ 25c sym parameter v cc 1 min max units conditions notes notes: 1. the v cc voltage speci?cation of 3.0v guarantees 3.0v; the v cc voltage speci?cation of 5.5v guarantees 5.0v 0.5v. 2. typical values are measured at v cc = 3.3v and v cc = 5.0v; v ss = 0v = gnd. 3. for the analog comparator input when the analog comparator is enabled. 4. no protection diode is provided from the pin to v cc . external protection is recommended. 5. all outputs are unloaded and all inputs are at the v cc or v ss level. 6. cl1 = cl2 = 22 pf. 7. same as note 5, except inputs are at v cc .
z8pe002 z8plus otp microcontroller zilog 12 p r e l i m i n a r y ds008700-z8x0799 dc electrical characteristics (continued) table 6. dc electrical characteristics t a = C40oc to +105oc extended temperatures typical 2 @ 25c sym parameter v cc 1 min max units conditions notes v ch clock input high voltage 4.5v 0.7 v cc v cc +0.3 2.5 v driven by external clock generator 5.5v 0.7 v cc v cc +0.3 2.5 v driven by external clock generator v cl clock input low voltage 4.5v v ss C0.3 0.2 v cc 1.5 v driven by external clock generator 5.5v v ss C0.3 0.2 v cc 1.5 v driven by external clock generator v ih input high voltage 4.5v 0.7 v cc v cc +0.3 2.5 v 5.5v 0.7 v cc v cc +0.3 2.5 v v il input low voltage 4.5v v ss C0.3 0.2 v cc 1.5 v 5.5v v ss C0.3 0.2 v cc 1.5 v v oh output high voltage 4.5v v cc C0.4 4.8 v i oh = C2.0 ma 5.5v v cc C0.4 4.8 v i oh = C2.0 ma v ol1 output low voltage 4.5v 0.4 0.1 v i ol = +4.0 ma 5.5v 0.4 0.1 v i ol = +4.0 ma v ol2 output low voltage 4.5v 1.2 0.5 v i ol = +12 ma 5.5v 1.2 0.5 v i ol = +12 ma v offset comparator input offset voltage 4.5v 25.0 10.0 mv 5.5v 25.0 10.0 mv i il input leakage 4.5v C1.0 2.0 <1.0 a v in = 0v, v cc 5.5v C1.0 2.0 <1.0 a v in = 0v, v cc i ol output leakage 4.5v C1.0 2.0 <1.0 a v in = 0v, v cc 5.5v C1.0 2.0 <1.0 a v in = 0v, v cc v icr comparator input common mode voltage range 4.5v 0 v cc C1.5v v 3 5.5v 0 v cc C1.5v v 3 r pb5 pb5 pull-up resistor 4.5v 100 200 kohm 4 5.5v 100 200 v lv v cc low-voltage protection 2.45 2.85 2.60 v i cc supply current 4.5v 7.0 4.0 ma @ 10 mhz 5,6 5.5v 7.0 4.0 ma @ 10 mhz 5,6 notes: 1. the v cc voltage speci?cation of 4.5v and 5.5v guarantees 5.0v 0.5v. 2. typical values are measured at v cc = 5.0v; v ss = 0v = gnd. 3. for analog comparator input when analog comparator is enabled. 4. no protection diode is provided from the pin to v cc . external protection is recommended. 5. all outputs are unloaded and all inputs are at v cc or v ss level. 6. cl1 = cl2 = 22 pf. 7. same as note 5, except inputs are at v cc .
z8pe002 zilog z8plus otp microcontroller ds008700-z8x0799 p r e l i m i n a r y 13 i cc1 standby current 4.5v 2.0 1.0 ma halt mode v in = 0v, v cc @ 10 mhz 5,6 5.5v 2.0 1.0 ma halt mode v in = 0v, v cc @ 10 mhz 5,6 i cc2 standby current 4.5v 700 250 na stop mode v in = 0v,v cc 7 5.5v 700 250 na stop mode v in = 0v,v cc 7 table 6. dc electrical characteristics (continued) t a = C40oc to +105oc extended temperatures typical 2 @ 25c sym parameter v cc 1 min max units conditions notes notes: 1. the v cc voltage speci?cation of 4.5v and 5.5v guarantees 5.0v 0.5v. 2. typical values are measured at v cc = 5.0v; v ss = 0v = gnd. 3. for analog comparator input when analog comparator is enabled. 4. no protection diode is provided from the pin to v cc . external protection is recommended. 5. all outputs are unloaded and all inputs are at v cc or v ss level. 6. cl1 = cl2 = 22 pf. 7. same as note 5, except inputs are at v cc .
z8pe002 z8plus otp microcontroller zilog 14 p r e l i m i n a r y ds008700-z8x0799 ac electrical characteristics figure 8. ac electrical timing diagram table 7. additional timing t a = 0oc to +70oc t a = C40oc to +105oc @ 10 mhz no symbol parameter v cc 1 min max units notes 1t p c input clock period 3.0v 100 dc ns 2 5.5v 100 dc ns 2 2t r c,t f c clock input rise and fall times 3.0v 15 ns 2 5.5v 15 ns 2 3t w c input clock width 3.0v 50 ns 2 5.5v 50 ns 2 4t w il int. request input low time 3.0v 70 ns 2 5.5v 70 ns 2 5t w ih int. request input high time 3.0v 5tpc 2 5.5v 5tpc 2 6t wsm stop mode recovery width spec. 3.0v 25 ns 5.5v 25 ns 7t ost oscillator start-up time 3.0v 5tpc 5.5v 5tpc 8t por power-on reset time 3.0v 128 t p c + t ost 5.5v notes: 1. the v dd voltage speci?cation of 3.0v guarantees 3.0v. the v dd voltage speci?cation of 5.5v guarantees 5.0v 0.5v. 2. timing reference uses 0.7 v cc for a logical 1 and 0.2 v cc for a logical 0. 1 3 4 2 2 3 5 clock irq n
z8pe002 zilog z8plus otp microcontroller ds008700-z8x0799 p r e l i m i n a r y 15 z8plus core the device is based on the zilog z8plus core architec- ture. this core is capable of addressing up to 32 kb of pro- gram memory and 4 kb of ram. register ram is accessed as either 8- or 16-bit registers using a combination of 4-, 8-, and 12-bit addressing modes. the architecture supports up to 15 vectored interrupts from external and internal sources. the processor decodes 44 cisc instructions using 6 addressing modes. see the z8plus users manual for more information. reset this section describes the z8plus reset conditions, reset timing, and register initialization procedures. reset is gen- erated by the voltage brown-out/power-on reset ( vbo/por ), watch-dog timer ( wdt ), and stop-mode recovery ( smr ). a system reset overrides all other operating conditions and puts the z8plus device into a known state. to initialize the chips internal logic, the por device counts 64 internal clock cycles after the oscillator stabilizes. the control reg- isters and ports are not reset to their default conditions after wakeup from a stop mode or wdt time-out. during reset , the value of the program counter is 0020h . the i/o ports and control registers are configured to their default reset state. resetting the device does not affect the contents of the general-purpose registers. the reset circuit initializes the control and peripheral reg- isters, as shown in table 8. specific reset values are indi- cated by a 1 or a 0 , while bits whose states are unchanged or unknown from power-up are indicated by the letter u . program execution starts 10 external crystal ( xtal ) clock cycles after the por delay. the initial instruction fetch is from location 0020h . figure 9 indicates reset timing. after a reset, the first routine executed must be one that ini- tializes the tctlhi control register to the required system configuration this activity is followed by initialization of the remaining control registers. table 8. control and peripheral registers* register (hex) register name bits comments 76543210 ff stack pointer 0 0 uuuuuu stack pointer is not affected by reset . fe reserved fd register pointer u u u u 0000 register pointer is not affected by reset . fc flags uuuuuu * * only wdt & smr ?ags are affected by reset . fb interrupt mask 00000000 all interrupts masked by reset . fa interrupt request 00000000 all interrupt requests cleared by reset . f9Cf0 reserved efCe0 virtual copy virtual copy of the current working register set. dfCd8 reserved d7 port b special function 00000000 deactivates all port special functions after reset . d6 port b directional control 00000000 de?nes all bits as inputs in portb after reset . d5 port b output uuuuuuuu output register not affected by reset . note: *the smr and wdt flags are set to indicate the source of the reset .
z8pe002 z8plus otp microcontroller zilog 16 p r e l i m i n a r y ds008700-z8x0799 reset (continued) d4 port b input uuuuuuuu current sample of the input pin following reset . d3 port a special function 00000000 deactivates all port special functions after reset . d2 port a directional control 00000000 de?nes all bits as inputs in porta after reset . d1 port a output uuuuuuuu output register not affected by reset d0 port a input uuuuuuuu current sample of the input pin following reset . cf reserved ce reserved cd t1val uuuuuuuu cc t0val uuuuuuuu cb t3val uuuuuuuu ca t2val uuuuuuuu c9 t3ar uuuuuuuu c8 t2ar uuuuuuuu c7 t1arhi uuuuuuuu c6 t0arhi uuuuuuuu c5 t1arlo uuuuuuuu c4 t0arlo uuuuuuuu c3 wdthi 11111111 c2 wdtlo 11111111 c1 tctlhi 11111000wdt enabled in halt mode, wdt time-out at maximum value, stop mode disabled. c0 tctllo 00000000 all standard timers are disabled. table 8. control and peripheral registers* (continued) register (hex) register name bits comments 76543210 note: *the smr and wdt flags are set to indicate the source of the reset . table 9. flag register bit d1, d0 d1 d0 reset source 00v bo /por 0 1 smr recovery 1 0 wdt reset 1 1 reserved
z8pe002 zilog z8plus otp microcontroller ds008700-z8x0799 p r e l i m i n a r y 17 figure 9. reset timing figure 10. reset circuitry with por, wdt, v bo , and smr first machine cycle clock internal first instruction fetch 128 xtal clock cycles 10 xtal clock cycles reset xtal 64 tctlhi d6,d5,d4 3 64 sclk smr (pb0) wdtrst 16-bit timer wdt tap select watch-dog timer smr logic v bo /por por delay
z8pe002 z8plus otp microcontroller zilog 18 p r e l i m i n a r y ds008700-z8x0799 interrupt sources table 10 presents the interrupt types, sources, and vectors available in the z8plus. other processors from the z8plus family may define the interrupts differently. external interrupt sources external sources can be generated by a transition on the cor- responding port pin. the interrupt may detect a rising edge, a falling edge, or both. notes: the interrupt sources and trigger conditions are device dependent. see the device product specification to de- termine available sources (internal and external), trig- gering edge options, and exact programming details. although interrupts are edge triggered, minimum inter- rupt request low and high times must be observed for proper operation. see the device product specification for exact timing requirements on external interrupt re- quests ( t w il , t w ih ). internal interrupt sources internal interrupt sources and trigger conditions are device dependent. on-chip peripherals may set interrupt under var- ious conditions. some peripherals always set their corre- sponding ireq bit while others must be specifically con- figured to do so. see the device product specification to determine available sources, triggering edge options, and exact programming details. for more details on the interrupt sources, refer to the chapters describing the timers, comparators, i/o ports, and other peripherals. interrupt mask register (imask) initialization the imask register individually or globally enables or dis- ables the interrupts (table 11). when bits 0 through 5 are set to 1 , the corresponding interrupt requests are enabled. bit 7 is the master enable bit and must be set before any of the individual interrupt requests can be recognized. reset- ting bit 7 disables all the interrupt requests. bit 7 is set and reset by the ei and di instructions. it is automatically set to 0 during an interrupt service routine and set to 1 following the execution of an interrupt return ( iret ) instruction. the imask registers are reset to 00h , disabling all interrupts. notes: it is not good programming practice to directly assign a value to the master enable bit. a value change should always be accomplished by issuing the ei and di in- structions. care should be taken not to set or clear imask bits while the master enable is set. table 10. interrupt types, sources, and vectors name sources vector location comments fixed priority ireq 0 timer0 time-out 2,3 internal 1 (highest) ireq 1 pb4 high-to-low transition 4,5 external (pb4), edge triggered 2 ireq 2 timer1 time-out 6,7 internal 3 ireq 3 pb2 high-to-low transition 8,9 external (pb2), edge triggered 4 ireq 4 pb4 low-to-high transition a,b external (pb4), edge triggered 5 ireq 5 timer2 time-out c,d internal 6 (lowest) ireq 6 Cireq 15 reserved reserved for future expansion
z8pe002 zilog z8plus otp microcontroller ds008700-z8x0799 p r e l i m i n a r y 19 interrupt request (ireq) register initialization ireq (table 12) is a register that stores the interrupt re- quests for both vectored and polled interrupts. when an in- terrupt is issued, the corresponding bit position in the reg- ister is set to 1 . bits 0 to 5 are assigned to interrupt requests ireq0 to ireq5 , respectively. whenever reset is executed, the ireq resistor is set to 00h . table 11. interrupt mask registerimask (fbh) bit 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 r = read w = write x = indeterminate u = unde?ned/ undetermined bit position r/w value description 7 0 1 disables interrupts enables interrupts 6 0 reserved, must be 0 5 0 1 disables irq5 enables irq5 4 0 1 disables irq4 enables irq4 3 0 1 disables irq3 enables irq3 2 0 1 disables irq2 enables irq2 1 0 1 disables irq1 enables irq1 0 0 1 disables irq0 enables irq0 table 12. interrupt request registerCireq (fah) bit 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 r = read w = write x = indeterminate u = unde?ned/ undetermined bit position r/w value description 7 r/w 0 reserved, must be 0 6 r/w 0 reserved, must be 0 5 r/w 0 1 irq5 reset irq5 set 4 r/w 0 1 irq4 reset irq4 set 3 r/w 0 1 irq3 reset irq3 set 2 r/w 0 1 irq2 reset irq2 set 1 r/w 0 1 irq1 reset irq1 set 0 r/w 0 1 irq0 reset irq0 set
z8pe002 z8plus otp microcontroller zilog 20 p r e l i m i n a r y ds008700-z8x0799 ireq software interrupt generation ireq can be used to generate software interrupts by spec- ifying ireq as the destination of any instruction referencing the z8plus standard register file. these software inter- rupts ( swi ) are controlled in the same manner as hardware generated requests. in other words, the imask controls the enabling of each swi . to generate a swi , the request bit in ireq is set by the fol- lowing statement: or ireq,#number the immediate data variable, number , has a 1 in the bit position corresponding to the required level of swi . for ex- ample, an swi must be issued when an ireq5 occurs. bit 5 of number must have a value of 1 . or ireq, #00100000b if the interrupt system is globally enabled, ireq5 is en- abled, and there are no higher priority requests pending, control is transferred to the service routine pointed to by the ireq5 vector. note: software may modify the ireq register at any time. care should be taken when using any instruction that modifies the ireq register while interrupt sources are active. the software writeback always takes precedence over the hardware. if a software writeback takes place on the same cycle as an interrupt source tries to set an ireq bit, the new interrupt is lost. nesting of vectored interrupts nesting vectored interrupts allows higher priority requests to interrupt a lower priority request. to initiate vectored in- terrupt nesting, perform the following steps during the in- terrupt service routine: ? push the old imask on the stack ? load imask with a new mask to disable lower prior- ity interrupts ? execute an ei instruction ? proceed with interrupt processing ? execute a di instruction after processing is complete ? restore the imask to its original value by pop ing the previous mask from the stack ? execute iret depending on the application, some simplification of the above procedure may be possible. reset conditions the imask and ireq registers initialize to 00h on reset . programmable options eprom protect. when selecting the disable eprom protect/enable testmode option, the user can read the software code in the program memory. zilogs inter- nal factory test mode, or any of the standard test mode meth- ods, are useful for reading or verifying the code in the mi- crocontroller when using an eprom programmer. if the user should select the enable eprom protect/dis- able testmode option, it is not possible to read the code using a tester, programmer, or any other standard method. as a result, zilog is unable to test the eprom memory at any time after customer delivery. this option bit only affects the users ability to read the code and has no effect on the operation of the part in an appli- cation. zilog tests the eprom memory before customer delivery whether or not the enable eprom pro- tect/disable testmode option is selected; zilog provides a standard warranty for the part. system clock source. when selecting the rc oscilla- tor enable option, the oscillator circuit on the micro- controller is configured to work with an external rc circuit. when selecting the crystal/other clock source option, the oscillator circuit is configured to work with an external crystal, ceramic resonator, or lc oscillator.
z8pe002 zilog z8plus otp microcontroller ds008700-z8x0799 p r e l i m i n a r y 21 watch-dog timer the watch-dog timer ( wdt ) is a retriggerable one-shot 16-bit timer that resets the device if it reaches its terminal count. the wdt is driven by the xtal2 clock pin. to pro- vide the longer time-out periods required in applications, the watch-dog timer is only updated every 64th clock cycle. when operating in the run or halt modes, a wdt time- out reset is functionally equivalent to an interrupt vectoring the pc to 0020h , and setting the wdt flag to 1 . coming out of reset , the wdt is fully enabled with its time-out value set at minimum, unless otherwise programmed during the first instruction. subsequent executions of the wdt in- struction reinitialize the watch-dog timer registers ( c2h and c3h ) to their initial values as defined by bits d6 , d5 , and d4 of the tctlhi register. the wdt cannot be disabled ex- cept on the first cycle after reset and when the device en- ters stop mode. the wdt instruction should be executed often enough to provide some margin of time to allow the wdt registers to approach 0 . because the wdt time-out periods are rela- tively long, a wdt reset occurs in the unlikely event that the wdt times out on exactly the same cycle that the wdt instruction is executed. reset clears both the wdt and smr flags. a wdt time- out sets the wdt flag, and the stop instruction sets the smr flag. this function enables software to determine whether a wdt time-out or a return from stop mode oc- curred. reading the wdt and smr flags does not reset the flag to 0 ; therefore, the user must clear the flag via software. note: failure to clear the smr flag can result in unexpected behavior. figure 11. tctlhi register for control of wdt d7 d6 d5 d4 d3 d2 d1 d0 0c1 tctlhi reserved (must be 0) 0 = stop mode enabled 1 = stop mode disabled* d6 d5 d4 wdt timeout value ---- ---- ---- -------------------------------- 0 0 0 disabled 0 0 1 65,536 tpc* 0 1 0 131,072 tpc 0 1 1 262,144 tpc 1 0 0 524,288 tpc 1 0 1 1,048,576 tpc 1 1 0 2,097,152 tpc 1 1 1 8,388,608 tpc (xtal clocks to time-out) 1 = wdt enabled in halt mode* 0 = wdt disabled in halt mode *designates the default value after reset .
z8pe002 z8plus otp microcontroller zilog 22 p r e l i m i n a r y ds008700-z8x0799 note: the wdt can only be disabled via software if the first in- struction out of the reset performs this function. logic within the device detects that it is in the process of exe- cuting the first instruction after the processor leaves re- set . during the execution of this instruction, the upper five bits of the tctlhi register can be written. after this first instruction, hardware does not allow the upper five bits of this register to be written. the tctlhi bits for control of the wdt are described be- low: wdt time select (d6, d5, d4). bits 6, 5, and 4 determine the time-out period. table 13 indicates the range of time- out values that can be obtained. the default values of d6 , d5 , and d4 are 001 , which sets the wdt to its minimum time-out period when coming out of reset . wdt during halt (d7). this bit determines whether or not the wdt is active during halt mode. a 1 indicates ac- tive during halt mode. a 0 prevents the wdt from reset- ting the part while halted. coming out of reset , the wdt is enabled during halt mode. stop mode (d3). coming out of reset , the device stop mode is disabled. if an application requires use of stop mode, bit d3 must be cleared immediately at leaving reset . if bit d3 is set, the stop instruction executes as a nop . if bit d3 is cleared, the stop instruction enters stop mode. bits 2, 1 and 0. these bits are reserved and must be 0 . power-down modes in addition to the standard run mode, the z8plus mcu supports two power-down modes to minimize device cur- rent consumption. the two modes supported are halt and stop . halt mode operation the halt mode suspends instruction execution and turns off the internal cpu clock. the on-chip oscillator circuit remains active so the internal clock continues to run and is applied to the timers and interrupt logic. to enter halt mode, the device only requires a halt in- struction. it is not necessary to execute a nop instruction immediately before the halt instruction. halt mode can be exited by servicing an external or inter- nal interrupt. the first instruction executed is the interrupt service routine. at completion of the interrupt service rou- tine, the user program continues from the instruction after the halt instruction. the halt mode can also be exited via a reset activation or a watch-dog timer ( wdt ) time-out. in these cases, pro- gram execution restarts at 0020h , the reset restart address. table 13. wdt time-out d6 d5 d4 crystal clocks* to timeout time-out using a 10-mhz crystal 0 0 0 disabled disabled 0 0 1 65,536 tpc 6.55 ms 0 1 0 131,072 tpc 13.11 ms 0 1 1 262,144 tpc 26.21 ms 1 0 0 524,288 tpc 52.43 ms 1 0 1 1,048,576 tpc 104.86 ms 1 1 0 2,097,152 tpc 209.72 ms 1 1 1 8,388,608 tpc 838.86 ms note: *tpc is an xtal clock cycle. the default at reset is 001. 7f halt ; enter halt mode
z8pe002 zilog z8plus otp microcontroller ds008700-z8x0799 p r e l i m i n a r y 23 stop mode operation the stop mode provides the lowest possible device stand- by current. this instruction turns off the on-chip oscillator and internal system clock. to enter the stop mode, the z8plus only requires a stop instruction. it is not necessary to execute a nop instruction immediately before the stop instruction. the stop mode is exited by any one of the following resets: por or a stop-mode recovery source. at reset generation, the processor always restarts the application program at ad- dress 0020h , and the stop mode flag is set. reading the stop mode flag does not clear it. the user must clear the stop mode flag with software. note: failure to clear the stop mode flag can result in unde- fined behavior. the z8plus provides a dedicated stop-mode recovery ( smr ) circuit. in this case, a low-level applied to input pin pb0 (i/o port b, bit 0) triggers an smr . to use this mode, pin pb0 must be configured as an input and the special func- tion selected before the stop mode is entered. the low level on pb0 must be held for a minimum pulse width t wsm . program execution starts at address 20h , after the por delay. notes: 1. the pb0 input, when used for stop-mode recovery, does not initialize the control registers. the stop mode current ( i cc2 ) is minimized when: ? v cc is at the low end of the devices operating range ? output current sourcing is minimized ? all inputs (digital and analog) are at the low or high rail voltages 2. for detailed information about flag settings, see the z8plus users manual . 6f stop ;enter stop mode
z8pe002 z8plus otp microcontroller zilog 24 p r e l i m i n a r y ds008700-z8x0799 clock the z8plus mcu derives its timing from on-board clock circuitry connected to pins xtal1 and xtal2 . the clock circuitry consists of an oscillator, a glitch filter, and a di- vide-by-two shaping circuit. figure 12 illustrates the clock circuitry. the oscillators input is xtal1 and its output is xtal2 . the clock can be driven by a crystal, a ceramic res- onator, lc clock, or an external clock source. by selecting the rc oscillator option in the graphical user interface (gui), the circuit may instead be driven by an external resistor and capacitor ( rc ) oscillator. figure 13 illustrates this configuration. this design is limited to no more than 4 mhz to restrict emi noise. note: the reduced drive strength of this configuration also al- lows the clock circuit to use a micropower-type crystal (also known as a tuning fork) without reduction resis- tors. figure 12. clock circuit 2 xtal2 xtal1 glitch filter 4 8 wdt clock timer clock (tclk) machine clock (sclk) (5 cycles per in- struction) figure 13. z8plus in rc oscillator mode glitch filter ss xtal2 xtal1 note: 4 mhz max. 2 r c v pin
z8pe002 zilog z8plus otp microcontroller ds008700-z8x0799 p r e l i m i n a r y 25 oscillator operation the z8plus mcu uses a pierce oscillator with an internal feedback resistor (figure 14). the advantages of this circuit are low-cost, large output signal, low-power level in the crystal, stability with respect to v cc and temperature, and low impedances (not disturbed by stray effects). one drawback to the pierce oscillator is the requirement for high gain in the amplifier to compensate for feedback path losses. the oscillator amplifies its own noise at start-up until it settles at the frequency that satisfies the gain/phase re- quirements. a x b = 1 ; where a = vo/vi is the gain of the amplifier, and b = vi/vo is the gain of the feedback element. the total phase shift around the loop is forced to 0 (360 de- grees). v in must be in phase with itself; therefore, the am- plifier/inverter provides a 180-degree phase shift, and the feedback element is forced to provide the other 180-degree phase shift. r1 is a resistive component placed from output to input of the amplifier. the purpose of this feedback is to bias the am- plifier in its linear region and provide the start-up transition. capacitor c2 , combined with the amplifier output resis- tance, provides a small phase shift. it also provides some attenuation of overtones. capacitor c 1 , combined with the crystal resistance, pro- vides an additional phase shift. start-up time may be affected if c 1 and c 2 are increased dra- matically in size. as c 1 and c 2 increase, the start-up time increases until the oscillator reaches a point where it ceases to operate. for fast and reliable oscillator start-up over the manufac- turing process range, the load capacitors should be sized as low as possible without resulting in overtone operation. layout traces connecting crystal, caps, and the z8plus oscillator pins should be as short and wide as possible to reduce par- asitic inductance and resistance. the components (caps, the crystal, and resistors) should be placed as close as possible to the oscillator pins of the z8plus. the traces from the oscillator pins of the integrated circuit (ic) and the ground side of the lead caps should be guarded from all other traces (clock, v cc , address/data lines, and system ground) to reduce cross talk and noise injection. guarding is usually accomplished by keeping other traces and system ground trace planes away from the oscillator cir- cuit, and by placing a z8plus device v ss ground ring around the traces/components. the ground side of the oscillator lead caps should be connected to a single trace to the z8plus device v ss (gnd) pin. it should not be shared with any other system-ground trace or components except at the z8plus device v ss pin. the objective is to prevent differential sys- tem ground noise injection into the oscillator (figure 15). indications of an unreliable design there are two major indicators that are used in working de- signs to determine their reliability over full lot and temper- ature variations. they are: start-up time. if start-up time is excessive, or varies widely from unit to unit, there is probably a gain problem. to fix the problem, the c 1 and c 2 capacitors require reduc- tion. the amplifier gain is either not adequate at frequency, or the crystal r s are too large. output level. the signal at the amplifier output should swing from ground to v cc to indicate adequate gain in the amplifier. as the oscillator starts up, the signal amplitude grows until clipping occurs. at that point, the loop gain is effectively reduced to unity, and constant oscillation is achieved. a signal of less than 2.5 volts peak-to-peak is an indication that low gain can be a problem. either c 1 or c 2 should be made smaller, or a low-resistance crystal should be used. figure 14. pierce oscillator with internal feedback circuit xtal2 z8plus v ss xtal1 c 1 c 2 r i v 1 a v 0
z8pe002 z8plus otp microcontroller zilog 26 p r e l i m i n a r y ds008700-z8x0799 oscillator operation (continued) circuit board design rules the following circuit board design rules are suggested: ? to prevent induced noise, the crystal and load capaci- tors should be physically located as close to the z8plus as possible. ? signal lines should not run parallel to the clock oscil- lator inputs. in particular, the crystal input circuitry and the internal system clock output should be separat- ed as much as possible. ? v cc power lines should be separated from the clock oscillator input circuitry. ? resistivity between xtal1 or xtal2 (and the other pins) should be greater than 10 meg-ohms. crystals and resonators crystals and ceramic resonators (figure 16) should exhibit the following characteristics to ensure proper oscillation: depending on the operation frequency, the oscillator may require additional capacitors, c 1 and c 2 , as illustrated in figure 16 and figure 17. the capacitance values are de- pendent on the manufacturers crystal specifications. figure 15. circuit board design rules xtal2 v ss xtal1 board design example v ss z8plus z8plus z8plus c 1 c 2 clock generator circuit signals a b signal c (parallel traces must be avoided) (top view) 17 16 15 17 16 xtal1 xtal2 x1 x2 pb0 v cc crystal cut at (crystal only) mode parallel, fundamental mode crystal capacitance <7pf load capacitance 10pf < cl < 220 pf, 15 typical resistance 100 ohms maximum
z8pe002 zilog z8plus otp microcontroller ds008700-z8x0799 p r e l i m i n a r y 27 in most cases, the r d is 0 ohms and r f is infinite. these specifications are determined and specified by the crys- tal/ceramic resonator manufacturer. the r d can be in- creased to decrease the amount of drive from the oscillator output to the crystal. it can also be used as an adjustment to avoid clipping of the oscillator signal to reduce noise. the r f can be used to improve the start-up of the crystal/ceramic resonator. the z8plus oscillator already locates an internal shunt resistor in parallel to the crystal/ceramic resonator. figure 16, figure 17, and figure 18 recommend that the load capacitor ground trace connect directly to the v ss (gnd) pin of the z8plus. this requirement assures that no system noise is injected into the z8plus clock. this trace should not be shared with any other components except at the v ss pin of the z8plus. note: a parallel-resonant crystal or resonator manufacturer specifies a load capacitor value that is a series combination of c 1 and c 2 , including all parasitics (pcb and holder). figure 16. crystal/ceramic resonator oscillator figure 17. lc clock xtal2 z8plus v ss xtal1 c 1 c 2 r f r d xtal2 z8plus v ss xtal1 c 1 c 2 l figure 18. external clock xtal2 z8plus v ss xtal1 n/c
z8pe002 z8plus otp microcontroller zilog 28 p r e l i m i n a r y ds008700-z8x0799 lc oscillator the z8plus oscillator can use an inductor capacitor oscil- lator ( lc ) network to generate an xtal clock (figure 17). the frequency stays stable over v cc and temperature. the oscillation frequency is determined by the equation: where l is the total inductance including parasitics, and c t is the total series capacitance including parasitics. simple series capacitance is calculated using the equation at the top of the next column. a sample calculation of capacitance c 1 and c 2 for 5.83- mhz frequency and inductance value of 27 h is displayed as follows: thus, c 1 = 55.2 pf and c 2 = 55.2 pf. timers two 8-bit timers, timer 0 ( t0) and timer 1 ( t1 ) are available to function as a pair of independent 8-bit standard timers. they may also be cascaded to function as a 16-bit pulse- width modulator (pwm) timer. two additional 8-bit tim- ers ( t2 and t3 ) are provided, but they can only operate as one 16-bit standard timer. frequency = 1 2 p ( lc t ) 1/2 1/ c t = 1/c 1 + 1/c 2 if c 1 =c 2 1/c t = 2/c 1 c 1 =2c t 5.83 (10^6) = 1 2 p [27 (10 -6 ) c t ] 1/2 c t = 27.6 pf figure 19. 16-bit standard timer enable tctll0 (d5) irq5 (t23) 16-bit down counter internal data bus t2val t3val osc/8 t3ar t2ar
z8pe002 zilog z8plus otp microcontroller ds008700-z8x0799 p r e l i m i n a r y 29 figure 20. 8-bit standard timers figure 21. 16-bit standard pwm timer enable tctll0 (d2?0) irq2 (t1) internal data bus osc/8 t1arhi t1arlo t1val 8-bit down counter (not used in this mode) 8-bit standard timer enable tctll0 (d2?0) irq2 (t0) internal data bus osc/8 t0arhi t0arlo t0val 8-bit down counter (not used in this mode) 8-bit standard timer 16-bit down counter internal data bus high side pwm low side t1arhi t1arlo irq0 irq2 t1val t1 t0 internal data bus t0arhi osc/8 t0arlo t0val edge detect logic t out
z8pe002 z8plus otp microcontroller zilog 30 p r e l i m i n a r y ds008700-z8x0799 timers (continued) a pair of read/write registers is utilized for each 8-bit timer. one register is defined to contain the auto-initializa- tion value for the timer. the second register contains the current value for the timer. when a timer is enabled, the tim- er decrements the value in its count register and continues decrementing until it reaches 0 . an interrupt is generated, and the contents of the auto-initialization register are op- tionally copied into the count value register. if auto-initial- ization is not enabled, the timer stops counting when the val- ue reaches 0 . control logic clears the appropriate control register bit to disable the timer. this operation is referred to as a single-shot . if auto-initialization is enabled, the timer counts from the initialization value. software must not at- tempt to use timer registers for any other function. user software is allowed to write to any write register at any time; however, care should be taken if timer registers are updated while the timer is enabled. if software changes the count value while the timer is in operation, the timer con- tinues counting from the updated value. note: unpredictable behavior can occur if the value updates at the same time that the timer reaches 0 . similarly, if user software changes the initialization value register while the timer is active, the next time that the timer reaches 0 , the timer initializes to the changed value. note: unpredictable behavior can occur if the initialization value register is changed while the timer is in the process of being initialized. the initialization value is determined by the exact timing of the write operation. in all cases, the z8plus assigns a higher priority to the software write than to a decrementer write-back. however, when hardware clears a control reg- ister bit for a timer that is configured for single-shot oper- ation, the clearing of the control bit overrides a software write . a read of either register can be conducted at any time, with no effect on the functionality of the timer. figure 22. tctllo register d7 d6 d5 d4 d3 d2 d1 d0 0c0 tctllo timer status d2 d1 d0 t0 t1 t01 ---- ---- ---- ------------- ------------- --------------- 0 0 0 disabled disabled 0 0 1 enabled disabled 0 1 0 disabled enabled 0 1 1 enabled enabled 1 0 0 enabled* 1 0 1 enabled* disabled 1 1 0 disabled enabled* 1 1 1 enabled* enabled* n ote : (*) indicates auto-reload is active. reserved (must be 0) 1 = t23 16-bit timer enabled with auto-reload active 0 = t2 and t3 timers disabled reserved (must be 0) note: timer t01 is a 16-bit pwm timer formed by cascading 8-bit timers t1 (msb) and t0 (lsb). t23 is a standard 16-bit timer formed by cascading 8-bit timers t3 (msb) and t2 (lsb).
z8pe002 zilog z8plus otp microcontroller ds008700-z8x0799 p r e l i m i n a r y 31 if a timer pair is defined to operate as a single 16-bit entity, the entire 16-bit value must reach 0 before an interrupt is generated. in this case, a single interrupt is generated, and the interrupt corresponds to the even 8-bit timer. example: timers t2 and t3 are cascaded to form a single 16- bit timer. the interrupt for the combined timer is defined to be generated by timer t2 rather than t3 . when a timer pair is specified to act as a single 16- bit timer, the even timer registers in the pair (timer t0 or t2 ) is defined to hold the timers least significant byte. in contrast, the odd timer in the pair holds the timers most significant byte. in parallel with the posting of the interrupt request, the in- terrupting timers count value is initialized by copying the contents of the auto-initialization value register to the count value register. note: any time that a timer pair is defined to act as a single 16- bit timer, the auto-reload function is performed automat- ically. all 16-bit timers continue counting while their interrupt re- quests are active and operate independently of each other. if interrupts are disabled for a long period of time, it is pos- sible for the timer to decrement to 0 again before its initial interrupt is responded to. this condition is termed a degen- erate case, and hardware is not required to detect it. when the timer control register is written, all timers that are enabled by the write begin counting from the value in the count register. in this case, an auto-initialization is not per- formed. all timers can receive an internal clock source input only. each enabled timer is updated every 8th xtal clock cycle. if t0 and t1 are defined to work independently, then each works as an 8-bit timer with a single auto-initialization reg- ister ( t0arlo for t0 , and t1arlo for t1 ). each timer as- serts its predefined interrupt when it times out, optionally performing the auto-initialization function. if t0 and t1 are cascaded to form a single 16-bit timer, then the single 16- bit timer is capable of performing as a pulse-width mod- ulator (pwm). this timer is referred to as t01 to distinguish it as having special functionality that is not available when t0 and t1 act independently. when t01 is enabled, it can use a pair of 16-bit auto-ini- tialization registers. in this mode, one 16-bit auto-initial- ization value is composed of the concatenation of t1arlo and t0arlo . the second auto-initialization value is com- posed of the concatenation of t1arhi and t0arhi . when t01 times out, it alternately initializes its count value using the low auto-init pair, followed by the high auto-init pair. this functionality corresponds to a pwm. that is, the t1 interrupt defines the end of the high section of the wave- form, and the t0 interrupt marks the end of the low portion of the pwm waveform. the pwm begins counting with whatever data is held in the count registers. after this value expires, the first reload de- pends on the state of the pb1 pin if t out mode is selected. otherwise, the low value is applied first. after the auto-initialization is completed, decrementing oc- curs for the number of counts defined by the pwm_lo reg- isters. when decrementing again reaches 0 , the t0 interrupt is asserted; and auto-init using the pwm_hi registers oc- curs. decrementing occurs for the number of counts defined by the pwm_hi registers until reaching 0 . from there, the t1 interrupt irq2 is asserted, and the cycle begins again. the internal timers can be used to trigger external events by toggling the pb1 output when generating an interrupt. this functionality can only be achieved in conjunction with the port unit defining the appropriate pin as an output signal with the timer output special function enabled. in this mode, the port output is toggled when the timer count reaches 0 , and continues toggling each time that the timer times out. t out mode the portb special function register ptbsfr ( 0d7h ; figure 23) is used in conjunction with the port b directional control register ptbdir ( 0d6 ; figure 24) to configure pb1 for t out operation for t0 . in order for t out to function, pb1 must be defined as an output line by setting ptbdir bit 1 to 1 . configured in this way, pb1 is capable of being a clock output for t0 , toggling the pb1 output pin on each t0 time- out. at end-of-count, the interrupt request line ( irq0 ), clocks a toggle flip-flop. the output of this flip-flop drives the t out line, pb1 . in all cases, when t0 reaches its end-of-count, t out toggles to its opposite state (figure 25). if, for exam- ple, t0 is in continuous counting mode, t out exhibits a 50-percent duty cycle output. if the timer pair is selected ( t01 ) as a pwm, the duty cycle depends on the high and low reload values. at the end of each high time, pb1 tog- gles low. at the end of each low time, pb1 toggles hi.
z8pe002 z8plus otp microcontroller zilog 32 p r e l i m i n a r y ds008700-z8x0799 timers (continued) figure 23. portb special function register figure 24. port b directional control register figure 25. timer t0 output through t out d7 d6 d5 d4 d3 d2 d1 d0 0d7 ptbsfr 1 = enable bit 0 as smr input 0 = no special functionality 1 = enable bit 1 as t0 output 0 = no special functionality 1 = enable bit 2 as irq2 input 0 = no special functionality d4 d3 comparator interrupts --- --- -------------- ------------------- 0 0 disabled disabled 0 1 enabled disabled 1 0 disabled enabled 1 1 enabled enabled bit 3: comparator reference input bit 4: comparator signal input/irq0/irq2 reserved (must be 0) d7 d6 d5 d4 d3 d2 d1 d0 0d6 ptbdir reserved (must be 0) 1 = bit n set as output 0 = bit n set as input t out pb1 irq0 (t0 end-of-count) ? 2
z8pe002 zilog z8plus otp microcontroller ds008700-z8x0799 p r e l i m i n a r y 33 reset conditions after a reset , the timers are disabled. see table 8 for timer control, value, and auto-initialization register status after reset . i/o ports the z8plus dedicates 14 lines to input and output. these lines are grouped into two ports known as port a and port b. port a is an 8-bit port, bit programmable as either inputs or outputs. port b can be programmed to provide either standard in- put/output, or the following special functions: t0 output, comparator input, smr input, and external interrupt inputs. all pins except pb5 include push-pull cmos outputs. in addition, the outputs of port a on a bit-wise basis can be configured for open-drain operation.the ports operate on a bit-wise basis. as such, the register values for/at a given bit position only affect the bit in question. each port is defined by a set of four control registers (figure 26). directional control and special function registers each port on the z8plus features a dedicated directional con- trol register that determines (on a bit-wise basis) if a given port bit operates as input or output. each port on the z8plus features a special function register ( sfr ) that, in conjunction with the directional control reg- ister , implements (on a bit-by-bit basis) any special func- tionality that can be defined for each particular port bit. input and output value registers each port features an output value register and an input value register. for port bits configured as an input by means of the directional control register , the input value register figure 26. port a con?guration with open-drain capability and schmitt-trigger pin pa0Cpa7 ptain bit n n = 0...7 ptaout bit n n = 0...7 ptasfr bit n n = 0...7 ptadir bit n n = 0...7 table 14. i/o ports registers register address identi?er port b special function 0d7h ptbsfr port b directional control 0d6h ptbdir port b output value 0d5h ptbout port b input value 0d4h ptbin port a special function 0d3h ptasfr port a directional control 0d2h ptadir port a output value 0d1h ptaout port a input value 0d0h ptain
z8pe002 z8plus otp microcontroller zilog 34 p r e l i m i n a r y ds008700-z8x0799 for that bit position contains the current synchronized input value. for port bits configured as an output by means of the di- rectional control register , the value held in the correspond- ing bit of the output value register is driven directly onto the output pin. the opposite register bit for a given pin (the output register bit for an input pin and the input register bit for an output pin) holds their previous value. these bits are not changed and do not exhibit any effect on the hardware. read/write operations the control for each port is done on a bit-by-bit basis. all bits are capable of operating as inputs or outputs, depending on the setting of the ports directional control register . if configured as an input, each bit is provided a schmitt-trig- ger. the output of the schmitt-trigger is latched twice to perform a synchronization function, and the output of the synchronizer is fed to the port input register, which can be read by software. a write to a port input register carries the effect of up- dating the contents of the input register, but subsequent reads do not necessarily return the same value that was written. if the bit in question is defined as an input, the input register for that bit position contains the current synchro- nized input value. writes to that bit position are overwrit- ten on the next clock cycle with the newly sampled input data. however, if the particular bit is programmed as an out- put, the input register for that bit retains the software-up- dated value. the port bits that are programmed as outputs do not sample the value being driven out. any bit in either port can be defined as an output by setting the appropriate bit in the directional control register . in this instance, the value held in the appropriate bit of the port out- put register is driven directly onto the output pin. note: the preceding result does not necessarily reflect the actual output value. if an external error is holding an output pin ei- ther high or low against the output driver, the software read returns the requested value, not the actual state caused by the contention. when a bit is defined as an output, the schmitt-trigger on the input is disabled to save power. updates to the output register take effect based on the timing of the internal instruction pipeline; however, this timing is referenced to the rising edge of the clock. the output reg- ister can be read at any time, and returns the current output value that is held. no restrictions are placed on the timing of reads and/or writes to any of the port registers with respect to the others. note: care should be taken when updating the directional con- trol and special function registers. when updating a directional control register, the special function register ( sfr ) should first be disabled. if this pre- caution is not taken, unpredicted events could occur as a re- sult of the change in the port i/o status. this precaution is especially important when defining changes in port b, as the unpredicted event referred to above could be one or more interrupts. clearing of the sfr register should be the first step in configuring the port, while setting the sfr reg- ister should be the final step in the port configuration pro- cess. to ensure unpredictable results, the sfr register should not be written until the pins are being driven appro- priately, and all initialization is completed. port a port a is a general-purpose port. figure 27 features a block diagram of port a. each of its lines can be independently programmed as input or output via the port a directional control register ( ptadir at 0d2h ) as seen in figure 26. a bit set to a 1 in ptadir configures the corresponding bit in port a as an output, while a bit cleared to 0 configures the corresponding bit in port a as an input. the input buffers are schmitt-triggered. bits programmed as outputs can be individually programmed as either push- pull or open-drain by setting the corresponding bit in the special function register ( ptasfr , figure 26). figure 27. port a directional control register d7 d6 d5 d4 d3 d2 d1 d0 0 = input 1 = output ptadir register register 0d2h
z8pe002 zilog z8plus otp microcontroller ds008700-z8x0799 p r e l i m i n a r y 35 port a register diagrams figure 28. port a input value register figure 29. port a output value register figure 30. port a directional control register figure 31. port a special function register d7 d6 d5 d4 d3 d2 d1 d0 register 0d0h ptain port a bit n current input value (only updated for pins in input mode) d7 d6 d5 d4 d3 d2 d1 d0 register 0d1h ptaout port a bit n currentoutput value d7 d6 d5 d4 d3 d2 d1 d0 register 0d2h ptadir 1 = bit n set as an output 0 = bit n set as an input d7 d6 d5 d4 d3 d2 d1 d0 register 0d3h ptasfr 1 = bit n in open-drain mode 0 = bit n in push-pull mode
z8pe002 z8plus otp microcontroller zilog 36 p r e l i m i n a r y ds008700-z8x0799 port b port b description port b is a 6-bit (bidirectional), cmos-compatible i/o port. these six i/o lines can be configured under software control to be an input or output. each bit is configured independently from the other bits. that is, one bit may be set to input while another bit is set to output . in addition to standard input/output capability, five pins of port b provide special functionality as indicated in table 15. special functionality is invoked via the port b special func- tion register. port b, bit 5, is an open-drain-only pin when in output mode. there is no high-side driver on the output stage, nor is there any high-side protection device, because pb5 acts as the v pp pin for eprom programming mode. the user should always place an external protection diode on this pin. see figure 32. table 15. port b special functions port pin input special function output special function pb0 stop mode recovery input none pb1 none t0 output pb2 irq3 none pb3 comparator reference input none pb4 comparator signal input/irq1/irq4 none figure 32. port b special function register d7 d6 d5 d4 d3 d2 d1 d0 register 0d7h ptbsfr 1 = enable pb0 as smr input 0 = no special functionality 1 = enable pb1 as t0 output 0 = no special functionality 1 = enable pb2 as irq3 input 0 = no special functionality reserved (must be 0) 1 = analog comparator on pb3 and pb4 0 = digital inputs on pb3 and pb4 1 = pb4 interrupts enabled 0 = pb4 interrupts disabled
z8pe002 zilog z8plus otp microcontroller ds008700-z8x0799 p r e l i m i n a r y 37 port bpin 0 configuration figure 33. port b pin 0 diagram figure 34. port b pin 5 diagram pin pb0 ptbout bit 0 ptbsfr bit 0 ptbdir bit 0 ptbdir bit 0 ptbin bit 0 smr smr flag reset pb5 ptbout bit 5 ptbdir bit 5 ptbdir bit 5 ptbin bit 5 pin approx 200 kohms v see note note: there is no high-side protection device. the user should always place an external protection diode as shown. cc
z8pe002 z8plus otp microcontroller zilog 38 p r e l i m i n a r y ds008700-z8x0799 port bpin 1 configuration figure 35. port b pin 1 diagram pin pb1 t0 output ptbout bit 1 ptbsfr bit 1 ptbdir bit 1 ptbdir bit 1 ptbin bit 1 m u x
z8pe002 zilog z8plus otp microcontroller ds008700-z8x0799 p r e l i m i n a r y 39 port bpin 2 configuration figure 36. port b pin 2 diagram pin pb2 ptbout bit 2 ptbsfr bit 2 ptbdir bit 2 ptbdir bit 2 ptbin bit 2 edge detect logic irq3
z8pe002 z8plus otp microcontroller zilog 40 p r e l i m i n a r y ds008700-z8x0799 port bpins 3 and 4 configuration figure 37. port b pins 3 and 4 diagram pin pb3 ptbout bit 3 ptbsfr bit 3 ptbdir bit 3 ptbdir bit 4 ptbin bit 4 edge detect logic irq1 irq4 + an in ref ptbdir bit 3 ptbin bit 3 pin pb4 ptbout bit 4 ptbdir bit 4 ptbsfr bit 4 m u x -
z8pe002 zilog z8plus otp microcontroller ds008700-z8x0799 p r e l i m i n a r y 41 port b control registers figure 38. port b input value register figure 39. port b output value register figure 40. port b directional control register d7 d6 d5 d4 d3 d2 d1 d0 register 0d4h ptbin port b bit n current input value reserved (must be 0) (only updated for pins in input mode) d7 d6 d5 d4 d3 d2 d1 d0 register 0d5h ptbout port b bit n current output value reserved (must be 0) d7 d6 d5 d4 d3 d2 d1 d0 register 0d6h ptbdir reserved (must be 0) 1 = bit n set as output 0 = bit n set as input
z8pe002 z8plus otp microcontroller zilog 42 p r e l i m i n a r y ds008700-z8x0799 port b control registers (continued) figure 41. port b special function register d7 d6 d5 d4 d3 d2 d1 d0 register 0d7h ptbsfr 1 = enable pb0 as smr input 0 = no special functionality 1 = enable pb1 as t0 output 0 = no special functionality 1 = enable pb2 as irq3 input 0 = no special functionality reserved (must be 0) 1 = analog comparator on pb3 and pb4 0 = digital inputs on pb3 and pb4 1 = pb4 interrupts enabled 0 = pb4 interrupts disabled
z8pe002 zilog z8plus otp microcontroller ds008700-z8x0799 p r e l i m i n a r y 43 i/o port reset conditions full reset port a and port b output value registers are not affected by reset . on reset , the port a and port b directional control reg- isters are cleared to all zeros, which defines all pins in both ports as inputs. on reset , the directional control registers redefine all pins as inputs, and the port a and port b input value registers overwrites the previously held data with the current sample of the input pins. on reset , the port a and port b special function registers are cleared to 00h , which deactivates all port special func- tions. note: the smr and wdt time-out events are not full device resets. the port control registers are not affected by ei- ther of these events. analog comparator the device includes one on-chip analog comparator. pin pb4 features a comparator front end. the comparator ref- erence voltage is on pin pb3 . comparator description the on-chip comparator can process an analog signal on pb4 with reference to the voltage on pb3 . the analog func- tion is enabled by programming the port b special function register bits 3 and 4. when the analog comparator function is enabled, bit 4 of the input register is defined as holding the synchronized out- put of the comparator, while bit 3 retains a synchronized sample of the reference input. if the interrupts for pb4 are enabled when the comparator special function is selected, the output of the comparator generates interrupts. comparator operation the comparator output reflects the relationship between the analog input to the reference input. if the voltage on the an- alog input is higher than the voltage on the reference input, then the comparator output is at a high state. if the voltage on the analog input is lower than the voltage on the reference input, then the analog output is at a low state. comparator definitions v icr the usable voltage range for the positive input and reference input is called the comparator input common mode voltage range ( v icr ). note: the comparator is not guaranteed to work if the input is outside of the v icr range. v offset the absolute value of the voltage between the positive input and the reference input required to make the comparator output voltage switch is the comparator input offset volt- age ( v offset ). i io for the cmos voltage comparator input, the input offset current ( i io ) is the leakage current of the cmos input gate. halt mode the analog comparator is functional during halt mode. if the interrupts are enabled, an interrupt generated by the comparator causes a return from halt mode. stop mode the analog comparator is disabled during stop mode. the comparator is powered down to prevent it from drawing any current. low voltage protection. an on-board voltage compar- ator checks that the v cc is at the required level to ensure correct operation of the device. a reset is globally driven if v cc is below the specified voltage (low voltage protec- tion). the device functions normally at or above 3.0v under all conditions, and is guaranteed to function normally at supply voltages above the low voltage protection trip point. be- low 3.0v, the device functions normally until the low volt-
z8pe002 z8plus otp microcontroller zilog 44 p r e l i m i n a r y ds008700-z8x0799 comparator operation (continued) age protection trip point ( v lv ) is reached. the actual low- voltage protection trip point is a function of process pa- rameters. low-voltage protection is active in run and halt modes only, but is disabled in stop mode (figure 42). figure 42. voltage vs. temperature v cc v olts) 2.80 2.40 2.20 2.00 1.80 1.60 ?0 ?0 ?0 0 20 40 60 80 100 120 140 3.00 2.60 temperature (?) typical v in run and halt modes lv
z8pe002 zilog z8plus otp microcontroller ds008700-z8x0799 p r e l i m i n a r y 45 input protection all i/o pins feature diode input protection. there is a diode from the i/o pad to v cc and v ss (figure 43). however, the pb5 pin features only the input protection di- ode, from the pad to v ss (figure 44). the high-side input protection diode was removed on this pin to allow the application of high voltage during the otp programming mode. for better noise immunity in applications that are exposed to system emi, a clamping diode to v ss from this pin should be used to prevent entering the otp programming mode or to prevent high voltage from damaging this pin. figure 43. i/o pin diode input protection pin v cc v ss figure 44. pb5 pin input protection pin v ss pb5
z8pe002 z8plus otp microcontroller zilog 46 p r e l i m i n a r y ds008700-z8x0799 package information figure 45. 18-pin dip package diagram figure 46. 18-pin soic package diagram
z8pe002 zilog z8plus otp microcontroller ds008700-z8x0799 p r e l i m i n a r y 47 figure 47. 20-pin ssop package diagram
z8pe002 z8plus otp microcontroller zilog 48 p r e l i m i n a r y ds008700-z8x0799 ordering information for fast results, contact your local zilog sales office for assistance in ordering the part(s) required. example: the z8pe002pz010sc is a 10-mhz dip, 0oc to 70oc, with plastic standard flow. pre-characterization product the product represented by this document is newly introduced and zilog has not completed the full characterization of the product. the document states what zilog knows about this product at this time, but additional features or non-conformance with some aspects of the document may be found, either by zilog or its customers in the course of further application and characterization work. in addition, zilog cautions that delivery may be uncertain at times, due to start-up yield issues. ?1999 by zilog, inc. all rights reserved. information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. except with the express written approval of zilog, use of information, devices, or technology as critical components of life support systems is not authorized. no licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights. zilog, inc. 910 east hamilton avenue, suite 110 campbell, ca 95008 telephone (408) 558-8500 fax 408 558-8300 internet: http://www.zilog.com standard temperature 18-pin dip z8pe002pz010sc 18-pin soic z8pe002sz010sc 20-pin ssop z8pe002hz010sc extended temperature 18-pin dip z8pe002pz010ec 18-pin soic Z8PE002SZ010EC 20-pin ssop z8pe002cz010ec codes preferred package pz = plastic dip longer lead time sz = soic hz = ssop speed 010 = 10 mhz standard temperature s = 0c to +70c extended temperature e = C40c to +105c environmental flow c = plastic standard z zilog pre?x 8pe z8plus product 002 product number pz package designation code 010 speed sc temperature and environmental flow

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